Capabilities and features of microprocessors vary widely, so the first step in trying to develop embedded software is to become familiar with the microprocessor's capabilities. Most manufacturers provide a programming card that describes the opcodes, mnemonics, addressing modes and registers. A large list of programming cards for various microprocessors is available from the web at: http://vmoc.museophile.com/cards/.
Let's examine the Z80 microprocessor in a bit more detail. For more information about the Z80 chip, including some designs that use it, visit http://www.geocities.com/SiliconValley/Peaks/3938/z80_home.htm.
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| |
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| Zilog |
| |
| ZZZZZZZ 88888 000 |
| Z 8 8 0 0 |
| Z 8 8 0 0 0 |
| Z 88888 0 0 0 |
| Z 8 8 0 0 0 |
| Z 8 8 0 0 |
| ZZZZZZZ 88888 000 |
| |
| Z80 MICROPROCESSOR Instruction Set Summary |
| |
| |
| |
| |
| |
| _________ _________ |
| _| \__/ |_ |
| <-- A11 |_|1 40|_| A10 --> |
| _| |_ |
| <-- A12 |_|2 39|_| A9 --> |
| _| |_ |
| <-- A13 |_|3 38|_| A8 --> |
| _| |_ |
| <-- A14 |_|4 37|_| A7 --> |
| _| |_ |
| <-- A15 |_|5 36|_| A6 --> |
| _| |_ |
| --> CLK |_|6 35|_| A5 --> |
| _| |_ |
| <--> D4 |_|7 34|_| A4 --> |
| _| |_ |
| <--> D3 |_|8 33|_| A3 --> |
| _| |_ |
| <--> D5 |_|9 32|_| A2 --> |
| _| |_ |
| <--> D6 |_|10 Z80 31|_| A1 --> |
| _| |_ |
| +5V |_|11 30|_| A0 --> |
| _| |_ |
| <--> D2 |_|12 29|_| GND |
| _| |_ ____ |
| <--> D7 |_|13 28|_| RFSH --> |
| _| |_ __ |
| <--> D0 |_|14 27|_| M1 --> |
| _| |_ _____ |
| <--> D1 |_|15 26|_| RESET <-- |
| ___ _| |_ _____ |
| --> INT |_|16 25|_| BUSRQ <-- |
| ___ _| |_ ____ |
| --> NMI |_|17 24|_| WAIT <-- |
| ____ _| |_ ____ |
| <-- HALT |_|18 23|_| BUSAK --> |
| ____ _| |_ __ |
| <-- MREQ |_|19 22|_| WR --> |
| ____ _| |_ __ |
| <-- IORQ |_|20 21|_| RD --> |
| |______________________| |
| |
| |
| |
| |
| |
| |
|Written by Jonathan Bowen |
| Programming Research Group |
| Oxford University Computing Laboratory |
| 8-11 Keble Road |
| Oxford OX1 3QD |
| England |
| |
| Tel +44-865-273840 |
| |
|Created August 1981 |
|Updated April 1985 |
|Issue 1.3 Copyright (C) J.P.Bowen 1985|
---------------------------------------------------------------
----------------------------------------------------------------
|Mnemonic |SZHPNC|Description |Notes |
|----------+------+---------------------+----------------------|
|ADC A,s |***V0*|Add with Carry |A=A+s+CY |
|ADC HL,ss |**?V0*|Add with Carry |HL=HL+ss+CY |
|ADD A,s |***V0*|Add |A=A+s |
|ADD HL,ss |--?-0*|Add |HL=HL+ss |
|ADD IX,pp |--?-0*|Add |IX=IX+pp |
|ADD IY,rr |--?-0*|Add |IY=IY+rr |
|AND s |***P00|Logical AND |A=A&s |
|BIT b,m |?*1?0-|Test Bit |m&{2^b} |
|CALL cc,nn|------|Conditional Call |If cc CALL |
|CALL nn |------|Unconditional Call |-[SP]=PC,PC=nn |
|CCF |--?-0*|Complement Carry Flag|CY=~CY |
|CP s |***V1*|Compare |A-s |
|CPD |****1-|Compare and Decrement|A-[HL],HL=HL-1,BC=BC-1|
|CPDR |****1-|Compare, Dec., Repeat|CPD till A=[HL]or BC=0|
|CPI |****1-|Compare and Increment|A-[HL],HL=HL+1,BC=BC-1|
|CPIR |****1-|Compare, Inc., Repeat|CPI till A=[HL]or BC=0|
|CPL |--1-1-|Complement |A=~A |
|DAA |***P-*|Decimal Adjust Acc. |A=BCD format |
|DEC s |***V1-|Decrement |s=s-1 |
|DEC xx |------|Decrement |xx=xx-1 |
|DEC ss |------|Decrement |ss=ss-1 |
|DI |------|Disable Interrupts | |
|DJNZ e |------|Dec., Jump Non-Zero |B=B-1 till B=0 |
|EI |------|Enable Interrupts | |
|EX [SP],HL|------|Exchange |[SP]<->HL |
|EX [SP],xx|------|Exchange |[SP]<->xx |
|EX AF,AF' |------|Exchange |AF<->AF' |
|EX DE,HL |------|Exchange |DE<->HL |
|EXX |------|Exchange |qq<->qq' (except AF)|
|HALT |------|Halt | |
|IM n |------|Interrupt Mode | (n=0,1,2)|
|IN A,[n] |------|Input |A=[n] |
|IN r,[C] |***P0-|Input |r=[C] |
|INC r |***V0-|Increment |r=r+1 |
|INC [HL] |***V0-|Increment |[HL]=[HL]+1 |
|INC xx |------|Increment |xx=xx+1 |
|INC [xx+d]|***V0-|Increment |[xx+d]=[xx+d]+1 |
|INC ss |------|Increment |ss=ss+1 |
|IND |?*??1-|Input and Decrement |[HL]=[C],HL=HL-1,B=B-1|
|INDR |?1??1-|Input, Dec., Repeat |IND till B=0 |
|INI |?*??1-|Input and Increment |[HL]=[C],HL=HL+1,B=B-1|
|INIR |?1??1-|Input, Inc., Repeat |INI till B=0 |
|JP [HL] |------|Unconditional Jump |PC=[HL] |
|JP [xx] |------|Unconditional Jump |PC=[xx] |
|JP nn |------|Unconditional Jump |PC=nn |
|JP cc,nn |------|Conditional Jump |If cc JP |
|JR e |------|Unconditional Jump |PC=PC+e |
|JR cc,e |------|Conditional Jump |If cc JR(cc=C,NC,NZ,Z)|
|LD dst,src|------|Load |dst=src |
|LD A,i |**0*0-|Load |A=i (i=I,R)|
|LDD |--0*0-|Load and Decrement |[DE]=[HL],HL=HL-1,# |
|LDDR |--000-|Load, Dec., Repeat |LDD till BC=0 |
|LDI |--0*0-|Load and Increment |[DE]=[HL],HL=HL+1,# |
|LDIR |--000-|Load, Inc., Repeat |LDI till BC=0 |
|NEG |***V1*|Negate |A=-A |
|NOP |------|No Operation | |
|OR s |***P00|Logical inclusive OR |A=Avs |
|OtdR |?1??1-|Output, Dec., Repeat |OUtd till B=0 |
|OTIR |?1??1-|Output, Inc., Repeat |OUTI till B=0 |
|OUT [C],r |------|Output |[C]=r |
|OUT [n],A |------|Output |[n]=A |
|OUtd |?*??1-|Output and Decrement |[C]=[HL],HL=HL-1,B=B-1|
|OUTI |?*??1-|Output and Increment |[C]=[HL],HL=HL+1,B=B-1|
|POP xx |------|Pop |xx=[SP]+ |
|POP qq |------|Pop |qq=[SP]+ |
|PUSH xx |------|Push |-[SP]=xx |
|PUSH qq |------|Push |-[SP]=qq |
|RES b,m |------|Reset bit |m=m&{~2^b} |
|RET |------|Return |PC=[SP]+ |
|RET cc |------|Conditional Return |If cc RET |
|RETI |------|Return from Interrupt|PC=[SP]+ |
|RETN |------|Return from NMI |PC=[SP]+ |
|RL m |**0P0*|Rotate Left |m={CY,m}<- |
|RLA |--0-0*|Rotate Left Acc. |A={CY,A}<- |
|RLC m |**0P0*|Rotate Left Circular |m=m<- |
|RLCA |--0-0*|Rotate Left Circular |A=A<- |
----------------------------------------------------------------
----------------------------------------------------------------
|Mnemonic |SZHPNC|Description |Notes |
|----------+------+---------------------+----------------------|
|RLD |**0P0-|Rotate Left 4 bits |{A,[HL]}={A,[HL]}<- ##|
|RR m |**0P0*|Rotate Right |m=->{CY,m} |
|RRA |--0-0*|Rotate Right Acc. |A=->{CY,A} |
|RRC m |**0P0*|Rotate Right Circular|m=->m |
|RRCA |--0-0*|Rotate Right Circular|A=->A |
|RRD |**0P0-|Rotate Right 4 bits |{A,[HL]}=->{A,[HL]} ##|
|RST p |------|Restart | (p=0H,8H,10H,...,38H)|
|SBC A,s |***V1*|Subtract with Carry |A=A-s-CY |
|SBC HL,ss |**?V1*|Subtract with Carry |HL=HL-ss-CY |
|SCF |--0-01|Set Carry Flag |CY=1 |
|SET b,m |------|Set bit |m=mv{2^b} |
|SLA m |**0P0*|Shift Left Arithmetic|m=m*2 |
|SRA m |**0P0*|Shift Right Arith. |m=m/2 |
|SRL m |**0P0*|Shift Right Logical |m=->{0,m,CY} |
|SUB s |***V1*|Subtract |A=A-s |
|XOR s |***P00|Logical Exclusive OR |A=Axs |
|----------+------+--------------------------------------------|
| F |-*01? |Flag unaffected/affected/reset/set/unknown |
| S |S |Sign flag (Bit 7) |
| Z | Z |Zero flag (Bit 6) |
| HC | H |Half Carry flag (Bit 4) |
| P/V | P |Parity/Overflow flag (Bit 2, V=overflow) |
| N | N |Add/Subtract flag (Bit 1) |
| CY | C|Carry flag (Bit 0) |
|-----------------+--------------------------------------------|
| n |Immediate addressing |
| nn |Immediate extended addressing |
| e |Relative addressing (PC=PC+2+offset) |
| [nn] |Extended addressing |
| [xx+d] |Indexed addressing |
| r |Register addressing |
| [rr] |Register indirect addressing |
| |Implied addressing |
| b |Bit addressing |
| p |Modified page zero addressing (see RST) |
|-----------------+--------------------------------------------|
|DEFB n(,...) |Define Byte(s) |
|DEFB 'str'(,...) |Define Byte ASCII string(s) |
|DEFS nn |Define Storage Block |
|DEFW nn(,...) |Define Word(s) |
|-----------------+--------------------------------------------|
| A B C D E |Registers (8-bit) |
| AF BC DE HL |Register pairs (16-bit) |
| F |Flag register (8-bit) |
| I |Interrupt page address register (8-bit) |
| IX IY |Index registers (16-bit) |
| PC |Program Counter register (16-bit) |
| R |Memory Refresh register |
| SP |Stack Pointer register (16-bit) |
|-----------------+--------------------------------------------|
| b |One bit (0 to 7) |
| cc |Condition (C,M,NC,NZ,P,PE,PO,Z) |
| d |One-byte expression (-128 to +127) |
| dst |Destination s, ss, [BC], [DE], [HL], [nn] |
| e |One-byte expression (-126 to +129) |
| m |Any register r, [HL] or [xx+d] |
| n |One-byte expression (0 to 255) |
| nn |Two-byte expression (0 to 65535) |
| pp |Register pair BC, DE, IX or SP |
| qq |Register pair AF, BC, DE or HL |
| qq' |Alternative register pair AF, BC, DE or HL |
| r |Register A, B, C, D, E, H or L |
| rr |Register pair BC, DE, IY or SP |
| s |Any register r, value n, [HL] or [xx+d] |
| src |Source s, ss, [BC], [DE], [HL], nn, [nn] |
| ss |Register pair BC, DE, HL or SP |
| xx |Index register IX or IY |
|-----------------+--------------------------------------------|
| + - * / ^ |Add/subtract/multiply/divide/exponent |
| & ~ v x |Logical AND/NOT/inclusive OR/exclusive OR |
| <- -> |Rotate left/right |
| [ ] |Indirect addressing |
| [ ]+ -[ ] |Indirect addressing auto-increment/decrement|
| { } |Combination of operands |
| # |Also BC=BC-1,DE=DE-1 |
| ## |Only lower 4 bits of accumulator A used |
----------------------------------------------------------------
Above you can see a programming card for Zilog's very popular Z80 microprocessor. This chip was widely used in the 1980's for various purposes including video games like Pacman, Galaxian, and many others. It was also used as the main processor for the Sega Master System. As other processors where developed that were faster and more capable, the Z80 was often used as a support processor in larger systems. For example, the Sega Genesis included a Z80 chip that was used exclusively to generate sounds for games. This meant the main processor could concentrate on the video graphics and game play without trying to also produce sounds at the same time.
Let's break down the example programming card, one section at a time:
--------------------------------------------------------------- | | | | | Zilog | | | | ZZZZZZZ 88888 000 | | Z 8 8 0 0 | | Z 8 8 0 0 0 | | Z 88888 0 0 0 | | Z 8 8 0 0 0 | | Z 8 8 0 0 | | ZZZZZZZ 88888 000 | | | | Z80 MICROPROCESSOR Instruction Set Summary | | | | | | | | | | | | _________ _________ | | _| \__/ |_ | | <-- A11 |_|1 40|_| A10 --> | | _| |_ | | <-- A12 |_|2 39|_| A9 --> | | _| |_ | | <-- A13 |_|3 38|_| A8 --> | | _| |_ | | <-- A14 |_|4 37|_| A7 --> | | _| |_ | | <-- A15 |_|5 36|_| A6 --> | | _| |_ | | --> CLK |_|6 35|_| A5 --> | | _| |_ | | <--> D4 |_|7 34|_| A4 --> | | _| |_ | | <--> D3 |_|8 33|_| A3 --> | | _| |_ | | <--> D5 |_|9 32|_| A2 --> | | _| |_ | | <--> D6 |_|10 Z80 31|_| A1 --> | | _| |_ | | +5V |_|11 30|_| A0 --> | | _| |_ | | <--> D2 |_|12 29|_| GND | | _| |_ ____ | | <--> D7 |_|13 28|_| RFSH --> | | _| |_ __ | | <--> D0 |_|14 27|_| M1 --> | | _| |_ _____ | | <--> D1 |_|15 26|_| RESET <-- | | ___ _| |_ _____ | | --> INT |_|16 25|_| BUSRQ <-- | | ___ _| |_ ____ | | --> NMI |_|17 24|_| WAIT <-- | | ____ _| |_ ____ | | <-- HALT |_|18 23|_| BUSAK --> | | ____ _| |_ __ | | <-- MREQ |_|19 22|_| WR --> | | ____ _| |_ __ | | <-- IORQ |_|20 21|_| RD --> | | |______________________| | | | | | | | | | | | | | |Written by Jonathan Bowen | | Programming Research Group | | Oxford University Computing Laboratory | | 8-11 Keble Road | | Oxford OX1 3QD | | England | | | | Tel +44-865-273840 | | | |Created August 1981 | |Updated April 1985 | |Issue 1.3 Copyright (C) J.P.Bowen 1985| ---------------------------------------------------------------
In the figure above, the name and manufacture of the microprocessor is given, followed by a pin-out of all the connections supported by the chip. Here is a detailed description of each of the pins shown.
| Pin | Label | Description |
|---|---|---|
| 1 | A11 | Output only; Memory address line 11 |
| 2 | A12 | Output only; Memory address line 12 |
| 3 | A13 | Output only; Memory address line 13 |
| 4 | A14 | Output only; Memory address line 14 |
| 5 | A15 | Output only; Memory address line 15 |
| 6 | CLK | Input only; Clock that makes the CPU work (usually about 4 MHz) |
| 7 | D4 | Input or Output; Data line 4 |
| 8 | D3 | Input or Output; Data line 3 |
| 9 | D5 | Input or Output; Data line 5 |
| 10 | D6 | Input or Output; Data line 6 |
| 11 | +5V | Power supply voltage connection |
| 12 | D2 | Input or Output; Data line 2 |
| 13 | D7 | Input or Output; Data line 7 |
| 14 | D0 | Input or Output; Data line 0 |
| 15 | D1 | Input or Output; Data line 1 |
| 16 | INT | Input only; Maskable-Interrupt line; Active when low; When asserted, the CPU stops running the current program and executes a special interrupt handler function. Can be disabled as needed. |
| 17 | NMI | Input only; Non-Maskable Interrupt; Active when low; When asserted, the CPU stops running the current program and executes a special interrupt handler function. Cannot be disabled. |
| 18 | HALT | Output only; CPU halted signal; Active when low |
| 19 | MREQ | Output only; Memory Request; Active when low; Asserted when data is being read from or written to RAM |
| 20 | IORQ | Output only; I/O Request; Active when low; Asserted when accessing an I/O port instead of RAM |
| 21 | RD | Output only; Memory read control; Active low; Asserted when reading data from memory |
| 22 | WR | Output only; Memory write control; Active low; Asserted when writing data to memory |
| 23 | BUSAK | Output only; Bus request acknowledgement; Active low; Allows another device to take over the bus |
| 24 | WAIT | Input only; Wait control; Active low; Used when accessing slow memory chips |
| 25 | BUSRQ | Input only; Bus Request; Active low; Signals CPU to stop accessing bus, so another device can control the bus; Works in conjunction with the BUSAK line. |
| 26 | RESET | Input only; CPU reset line; Active low; Normally set low briefly during the power up cycle. Can be attached to a reset switch. |
| 27 | M1 | Output only; Memory fetch line; Active low; Asserted when reading a CPU instruction from memory, as opposed to a normal byte of data. |
| 28 | RFSH | Output only; Refresh timing control; Active low; Asserted while the CPU is busy refreshing RAM. |
| 29 | GND | Power supply ground connection |
| 30 | A0 | Output only; Memory address line 0 |
| 31 | A1 | Output only; Memory address line 1 |
| 32 | A2 | Output only; Memory address line 2 |
| 33 | A3 | Output only; Memory address line 3 |
| 34 | A4 | Output only; Memory address line 4 |
| 35 | A5 | Output only; Memory address line 5 |
| 36 | A6 | Output only; Memory address line 6 |
| 37 | A7 | Output only; Memory address line 7 |
| 38 | A8 | Output only; Memory address line 8 |
| 39 | A9 | Output only; Memory address line 9 |
| 40 | A10 | Output only; Memory address line 10 |
Next we have the commands recognized by the CPU, with detailed information listed to the right of the mnemonic. They are generally self-explanatory and when working in assembly language, the mnemonics are entered into your source code. The column named SZHPNC describes the effect on the flags register each instruction has. The will be covered more fully in a moment.
----------------------------------------------------------------
|Mnemonic |SZHPNC|Description |Notes |
|----------+------+---------------------+----------------------|
|ADC A,s |***V0*|Add with Carry |A=A+s+CY |
|ADC HL,ss |**?V0*|Add with Carry |HL=HL+ss+CY |
|ADD A,s |***V0*|Add |A=A+s |
|ADD HL,ss |--?-0*|Add |HL=HL+ss |
|ADD IX,pp |--?-0*|Add |IX=IX+pp |
|ADD IY,rr |--?-0*|Add |IY=IY+rr |
|AND s |***P00|Logical AND |A=A&s |
|BIT b,m |?*1?0-|Test Bit |m&{2^b} |
|CALL cc,nn|------|Conditional Call |If cc CALL |
|CALL nn |------|Unconditional Call |-[SP]=PC,PC=nn |
|CCF |--?-0*|Complement Carry Flag|CY=~CY |
|CP s |***V1*|Compare |A-s |
|CPD |****1-|Compare and Decrement|A-[HL],HL=HL-1,BC=BC-1|
|CPDR |****1-|Compare, Dec., Repeat|CPD till A=[HL]or BC=0|
|CPI |****1-|Compare and Increment|A-[HL],HL=HL+1,BC=BC-1|
|CPIR |****1-|Compare, Inc., Repeat|CPI till A=[HL]or BC=0|
|CPL |--1-1-|Complement |A=~A |
|DAA |***P-*|Decimal Adjust Acc. |A=BCD format |
|DEC s |***V1-|Decrement |s=s-1 |
|DEC xx |------|Decrement |xx=xx-1 |
|DEC ss |------|Decrement |ss=ss-1 |
|DI |------|Disable Interrupts | |
|DJNZ e |------|Dec., Jump Non-Zero |B=B-1 till B=0 |
|EI |------|Enable Interrupts | |
|EX [SP],HL|------|Exchange |[SP]<->HL |
|EX [SP],xx|------|Exchange |[SP]<->xx |
|EX AF,AF' |------|Exchange |AF<->AF' |
|EX DE,HL |------|Exchange |DE<->HL |
|EXX |------|Exchange |qq<->qq' (except AF)|
|HALT |------|Halt | |
|IM n |------|Interrupt Mode | (n=0,1,2)|
|IN A,[n] |------|Input |A=[n] |
|IN r,[C] |***P0-|Input |r=[C] |
|INC r |***V0-|Increment |r=r+1 |
|INC [HL] |***V0-|Increment |[HL]=[HL]+1 |
|INC xx |------|Increment |xx=xx+1 |
|INC [xx+d]|***V0-|Increment |[xx+d]=[xx+d]+1 |
|INC ss |------|Increment |ss=ss+1 |
|IND |?*??1-|Input and Decrement |[HL]=[C],HL=HL-1,B=B-1|
|INDR |?1??1-|Input, Dec., Repeat |IND till B=0 |
|INI |?*??1-|Input and Increment |[HL]=[C],HL=HL+1,B=B-1|
|INIR |?1??1-|Input, Inc., Repeat |INI till B=0 |
|JP [HL] |------|Unconditional Jump |PC=[HL] |
|JP [xx] |------|Unconditional Jump |PC=[xx] |
|JP nn |------|Unconditional Jump |PC=nn |
|JP cc,nn |------|Conditional Jump |If cc JP |
|JR e |------|Unconditional Jump |PC=PC+e |
|JR cc,e |------|Conditional Jump |If cc JR(cc=C,NC,NZ,Z)|
|LD dst,src|------|Load |dst=src |
|LD A,i |**0*0-|Load |A=i (i=I,R)|
|LDD |--0*0-|Load and Decrement |[DE]=[HL],HL=HL-1,# |
|LDDR |--000-|Load, Dec., Repeat |LDD till BC=0 |
|LDI |--0*0-|Load and Increment |[DE]=[HL],HL=HL+1,# |
|LDIR |--000-|Load, Inc., Repeat |LDI till BC=0 |
|NEG |***V1*|Negate |A=-A |
|NOP |------|No Operation | |
|OR s |***P00|Logical inclusive OR |A=Avs |
|OtdR |?1??1-|Output, Dec., Repeat |OUtd till B=0 |
|OTIR |?1??1-|Output, Inc., Repeat |OUTI till B=0 |
|OUT [C],r |------|Output |[C]=r |
|OUT [n],A |------|Output |[n]=A |
|OUtd |?*??1-|Output and Decrement |[C]=[HL],HL=HL-1,B=B-1|
|OUTI |?*??1-|Output and Increment |[C]=[HL],HL=HL+1,B=B-1|
|POP xx |------|Pop |xx=[SP]+ |
|POP qq |------|Pop |qq=[SP]+ |
|PUSH xx |------|Push |-[SP]=xx |
|PUSH qq |------|Push |-[SP]=qq |
|RES b,m |------|Reset bit |m=m&{~2^b} |
|RET |------|Return |PC=[SP]+ |
|RET cc |------|Conditional Return |If cc RET |
|RETI |------|Return from Interrupt|PC=[SP]+ |
|RETN |------|Return from NMI |PC=[SP]+ |
|RL m |**0P0*|Rotate Left |m={CY,m}<- |
|RLA |--0-0*|Rotate Left Acc. |A={CY,A}<- |
|RLC m |**0P0*|Rotate Left Circular |m=m<- |
|RLCA |--0-0*|Rotate Left Circular |A=A<- |
|RLD |**0P0-|Rotate Left 4 bits |{A,[HL]}={A,[HL]}<- ##|
|RR m |**0P0*|Rotate Right |m=->{CY,m} |
|RRA |--0-0*|Rotate Right Acc. |A=->{CY,A} |
|RRC m |**0P0*|Rotate Right Circular|m=->m |
|RRCA |--0-0*|Rotate Right Circular|A=->A |
|RRD |**0P0-|Rotate Right 4 bits |{A,[HL]}=->{A,[HL]} ##|
|RST p |------|Restart | (p=0H,8H,10H,...,38H)|
|SBC A,s |***V1*|Subtract with Carry |A=A-s-CY |
|SBC HL,ss |**?V1*|Subtract with Carry |HL=HL-ss-CY |
|SCF |--0-01|Set Carry Flag |CY=1 |
|SET b,m |------|Set bit |m=mv{2^b} |
|SLA m |**0P0*|Shift Left Arithmetic|m=m*2 |
|SRA m |**0P0*|Shift Right Arith. |m=m/2 |
|SRL m |**0P0*|Shift Right Logical |m=->{0,m,CY} |
|SUB s |***V1*|Subtract |A=A-s |
|XOR s |***P00|Logical Exclusive OR |A=Axs |
-----------+------+---------------------------------------------
After the command set for the CPU, the next section of the programming card describes the meanings of the SZHPNC flags. The sample card describes what effect each instruction has on the following flags (stored in the special flags register).
The 'F' line describes that a - means the command has no effect on the flag. An '*' in a column means the flag will be set or clear depending on the results of the command. A '0' indicates that the flag will always be reset, while a '1' means the flag will always be set. A 'P' or a 'V' in a column means that the command will set the flag if a parity error is detected, or if an overflow is detected. Finally, a '?' means the flag may be changed by the command, but the exact value the flag will contain is not known.
For example, the mnemonic for one of the ADD instructions looks like this:
---------------------------------------------------------------- |Mnemonic |SZHPNC|Description |Notes | |----------+------+---------------------+----------------------| |ADD A,s |***V0*|Add |A=A+s | -----------+------+---------------------------------------------
This command takes the number already in the general-purpose 'A' register and adds some other value 's' to it. It then stores the result back into the 'A' register. Since there is a 'V' under the 'P' column, then means the 'Parity' flag register will be set if an overflow occurs. The '0' under the 'N' column means the 'Add/Subtract' flag will always be reset. All other flags in the flag register will not be changed.
An overflow occurs if you attempt to add two values together that are larger than the register can hold. With 8-bit registers, the maximum value the register can hold is 2^8 - 1, or 255, while 16-bit registers can hold a value up to 2^16 - 1, or 65,535 and 32-bit registers can hold up to 2^32 - 1, or 4,294,967,295.
NOTE: At this point, you might say, well what about signed versus unsigned values? Good question. The way processors are designed to perform mathematically operations on values, the CPU does not care if the number is signed or unsigned. The same steps used to add two positive numbers works when adding two negative numbers. The way you usage the values determines if they are signed or unsigned. It does not affect the way the operations are carried out by the processor internally.
The next section of our microprocessor card describes the various addressing modes the CPU supports. Our example card lists the following addressing modes:
|-----------------+--------------------------------------------| | n |Immediate addressing | | nn |Immediate extended addressing | | e |Relative addressing (PC=PC+2+offset) | | [nn] |Extended addressing | | [xx+d] |Indexed addressing | | r |Register addressing | | [rr] |Register indirect addressing | | |Implied addressing | | b |Bit addressing | | p |Modified page zero addressing (see RST) | |-----------------+--------------------------------------------|
So, in the mnemonic section, a parameter that shows 'n' means the value supplied is treated as an exact memory address.
For Example: IN A,[n]
This instruction means read a byte of data from memory address 'n' and store it in register 'A'. IN stands for the Input command.
A parameter listed as 'nn' is also a fixed address, but it is mostly used by commands that affect the CPU's program counter (PC) register. The CPU keeps track of the next instruction to run by examining the PC register. After each instruction is executed, the PC register is moved forward to point to the next instruction in sequence.
For Example: JP nn
This example means transfer control of the program to memory location 'nn'. This affects the PC register and changes the address of where the next instruction is read from memory. JP stands for the Jump command. (If this sounds like a GOTO command, you are correct.)
A parameter of 'e' is another special kind of address similar in some was to the 'nn' parameters, except it is used as an offset that is combined with the current value of the PC register.
For Example: JR 'e'
This example means transfer control 'e' bytes forward (or backward) from the current location held in the PC register. It is generally used for making a small jump to a spot in your code that is close to the current instructions. The benefit of using JR instead of JP is that the 'e' parameter is normally 1 byte long, while the 'nn' parameter is 2-bytes (or more). This means the JR command takes up only 2 bytes of memory, while JP requires at least 3 bytes.
A '[nn]' parameter is used to indicate that the command supports retrieving a memory address that is stored in a memory location, and then uses that memory address to complete the command. Programmers familiar with the concept of pointers should recognize this as a kind of pointer dereferencing or pointer lookup, because that is exactly what it means.
A '[xx+d]' parameter is similar to the '[nn]' parameters, but with one small difference. In this case, it means load a memory address stored in memory location 'xx[d]', so it is like accessing an array of memory locations, where 'xx' is the array and 'd' is the offset within the array. This can be used as the basis for a kind of switch statement that C programmers are probably familiar with.
A parameter of 'r' indicates that one of the registers will be used to complete the instruction. In this case, the Z80 processor actually two sets of registers. This parameter means use registers A, B, C, D, E, H or L.
An '[rr]' parameter means that one of the registers holds a memory address, which should be used to complete the instruction. This is another form of pointer indirection or dereferencing.
A 'b' parameters means to use a bit offset to complete the instruction. This is needed mostly for commands that manipulate one bit in a word or byte.
Example: SET b,m
This causes the processor to turn on (set to 1) the single 'b' bit in register 'm'.
A 'p' parameter is a special pointer only used with the RST command. It tells the processor to enter an interrupt handler, where 'p' can be 0h, 8h, 10h, 18h, 20h, 28h, 30h, or 38h.
The next section of the programming card is assembly language instructions and is not part of the CPU instruction set at all. Instead, they document features of the assembler tool used to create programs for the CPU. In our card, the following commands are used to create constant arrays of bytes, characters, words or strings that can be used throughout the program as needed.
------------------+--------------------------------------------- |DEFB n(,...) |Define Byte(s) | |DEFB 'str'(,...) |Define Byte ASCII string(s) | |DEFS nn |Define Storage Block | |DEFW nn(,...) |Define Word(s) | ------------------+---------------------------------------------
The next section of the programming card documents the registers in the Z80 microprocessor. As you can see, the Z80 has 5 general-purpose 8-bit registers, 4 general-purpose 16-bit registers, one flag register, one interrupt page address register, 2 index registers, a program counter register, a memory refresh register and a stack pointer register.
------------------+--------------------------------------------- | A B C D E |Registers (8-bit) | | AF BC DE HL |Register pairs (16-bit) | | F |Flag register (8-bit) | | I |Interrupt page address register (8-bit) | | IX IY |Index registers (16-bit) | | PC |Program Counter register (16-bit) | | R |Memory Refresh register | | SP |Stack Pointer register (16-bit) | ------------------+---------------------------------------------
Registers A, B, C, D and E are all 8-bits wide, so they are suitable for holding values between 0 and 255. These registers can be joined with another 8-bit register to form a 16-bit register.
Registers AF, BC, ED and HL are 16-bits wide, so they are suitable for holding values between 0 and 65535. Combining two 8-bit registers makes up most of the 16-bit registers, which has an important side effect. When using register BC for example, the lower 8 bits of the 16 bit value will be stored in register C, while the upper 8 bits are stored in B.
The flag register 'F' is used to hold status information about the last instruction executed by the microprocessor. For example, when adding two values together, the 'V' bit in the flag register will be set to indicate an overflow, should this occur. The flag register bits are tested with the conditional version of the JR, JP, CALL and RET instructions.
The 'IX' and 'IY' are used mainly as pointers (or offsets) to data structures. It is then possible to walk through a data structure using this offsets, incrementing or decrementing the index pointer register each time.
The 'PC' register is used by the microprocessor to track the memory address where the microprocessor should fetch its next instruction. During program execution, the 'PC' counter is automatically advanced as each instruction is executed. It's current value is modified when using the CALL or JP commands.
The 'R' register is a special-purpose register used by the microprocessor for RAM memory refresh cycles.
The 'SP' register is also a special-purpose register. It tracks a small block of memory used during CALL instructions. When executing a 'CALL' command, the microprocessor must remember where the 'CALL' originated from, so it can later return to that section of code, once it reaches a 'RET' instruction. In addition, the stack is used for creating local variables and storing function call parameters. The stack is normally manipulated using the PUSH and POP commands, which load or store a new value on the stack and increment or decrement the 'SP' register as needed. Within a function, parameters are usually read from the stack using the LD command.
Finally, the last section of the programming card details the parameters and operations listed under the instruction set shown earlier. So for example, any operation that shows 'pp' in the table, means you can use any of the registers BC, DE, IX or SP as an argument to the instruction.
|-----------------+--------------------------------------------|
| b |One bit (0 to 7) |
| cc |Condition (C,M,NC,NZ,P,PE,PO,Z) |
| d |One-byte expression (-128 to +127) |
| dst |Destination s, ss, [BC], [DE], [HL], [nn] |
| e |One-byte expression (-126 to +129) |
| m |Any register r, [HL] or [xx+d] |
| n |One-byte expression (0 to 255) |
| nn |Two-byte expression (0 to 65535) |
| pp |Register pair BC, DE, IX or SP |
| qq |Register pair AF, BC, DE or HL |
| qq' |Alternative register pair AF, BC, DE or HL |
| r |Register A, B, C, D, E, H or L |
| rr |Register pair BC, DE, IY or SP |
| s |Any register r, value n, [HL] or [xx+d] |
| src |Source s, ss, [BC], [DE], [HL], nn, [nn] |
| ss |Register pair BC, DE, HL or SP |
| xx |Index register IX or IY |
|-----------------+--------------------------------------------|
| + - * / ^ |Add/subtract/multiply/divide/exponent |
| & ~ v x |Logical AND/NOT/inclusive OR/exclusive OR |
| <- -> |Rotate left/right |
| [ ] |Indirect addressing |
| [ ]+ -[ ] |Indirect addressing auto-increment/decrement|
| { } |Combination of operands |
| # |Also BC=BC-1,DE=DE-1 |
| ## |Only lower 4 bits of accumulator A used |
----------------------------------------------------------------
Here is an example project that uses the Z80 microprocessor to create a minimal computer system that can be used as an embedded controller. Project details are available online from http://www.geocities.com/SiliconValley/Peaks/3938/z80_mp.htm.
The parts required to build this small computer are:
Minimal Z80 Board - Mario Prato - December 1997
for any information: E.mail mprato@iqsnet.it
This is my Z80 board :
# CPU Z80 at 4MHz (U6)
# RAM 32 Kbytes with battery backup (U8)
# ROM 8 Kbytes (U7)
# Clock generator (U2)
# Address Decoder (U5)
# 8 bit Output Port (U4)
# 8 bit Input Port (U3)
# 5V Voltage Regulator (U1)
Power supply:
Power supply of the board can be any voltage between 7 to 25 Volt but it is better to stay below 15 V.
Voltage regulator U1 must be mounted on a heat radiator.
Memory map:
System ROM is located from address 0000h to 1FFFh (8K), RAM start from 8000h to FFFFh (32K).
The only I/O address is 001H from that you can read/write to external ports.
+--------+--------+----------------+
| rom | n.u. | ram |
| | | |
+--------+--------+----------------+
0000H 1FFFH 8000H FFFFH
IO map:
00h read not used (select signal on U5 pin 5 is free for future use)
00h write not used (select signal on U5 pin 4 is free for future use)
01h read input port
01h write output port
Building the board:
You can mount all the components on a prototype board, but if you have enough
experience with PCB, you can use the tracks I give you. My
PCB is a dual face with no passing through holes, so before the
insertion of the components, you need to connect the traces of the component side with
copper side.
Component List
BT1 lithium battery 3.6 Volt
C1,C2 100uF 25V electrolytic
C3,C4,C5 100nF polyester
C6 100pF Ceramic
C7 1uF 16V electrolytic
D2,D3,D4,D5 1n914 o 1n4148 small signal silicon diode
J1,J2 strip-line connector 10 pin step 2.54mm (0.1 in)
J3 connector 2 pin step 5mm (0.2 in)
R1 10K 1/8W
R3 330 1/8W
R4,R5 1200 1/8W
R6 220K 1/8W
U1 uA7805 or LM7805 (in TO-220 on heat sink)
U2 74LS04 inverter
U3 74LS244 buffer
U4 74LS374 latch
U5 74LS139 decoder
U6 Z80A CPU (CMOS version)
U7 27C64 eprom 8k x 8
U8 AT28C256 or 62256 ram 32k x 8
Y1 Quartz crystal 4 MHz
Very important:
Capacitors c3,c4,c5 are useful to decouple power supply rail, but due to the small
space available on the board they maybe inserted on the copper side
or on the I.C. sockets. Refer to the schematics.
If you don't want to use the battery backup feature don't
mount R1 and D4. short D5 and D3.
It is a good idea is to mount a push button across C7 so you can reset the CPU.